1. Field of the Invention
The present invention relates to assessing integrity of a high speed signal at a receiver on an integrated circuit chip.
2. Background of the Related Art
Clock frequencies of computer systems continue to increase, leading to a corresponding increase in the input/output (I/O) frequencies in today's high speed computer systems. Various interfaces in a high speed system, such as multi-drop interfaces like memory (e.g. DDR-3) and serial interfaces such as PCIe (Peripheral Component Interconnect Express), SAS (Serial Attached SCSI), and GbE (Gigabit Ethernet), are capable of transferring data on the order of Gigabits per second. Assessing the signal integrity at the receiver, in terms of characteristics such as rise time and fall time, is an important part of verifying the expected operation of a chip. However, performing measurements on such high speed systems is increasingly challenging, particularly due to anomalies that can occur at higher signal speeds, such as signal reflections.
Accurately measuring a signal received in a chip is challenging because the signal is typically received at a point that is internal to the chip package, and is not directly accessible to peripheral testing equipment. To measure the signal, the signal is typically conducted from a pad on the chip to a corresponding package pin, and the signal is probed at the pin rather than directly on the chip. When probing at the package pin in a conventional manner, the resultant measurement is not a true representation of the original signal waveform as it is received at the chip. For example, measurements at the package pin may show artifacts that are not actually present at the receiver pad. For example, such artifacts may manifest as a slope reversal, which may be significant enough to obscure the correct interpretation of the signal.